Voltage level translator

ABSTRACT

A translator includes an initial circuit device configured to charge a translator output to a first voltage level in response to a change in an input signal. The translator further includes a sensing device configured to detect the output&#39;s potential approaching the first voltage level and smoothly shift charging functions over to a secondary circuit device, which will continue to charge the output up to a second voltage level.

RELATED APPLICATIONS

[0001] This application is a continuation of U.S. application Ser. No.09/691,415, filed Oct. 17, 2000; which is a continuation of U.S.application Ser. No. 09/327,040, filed Jun. 7, 1999 and issued as U.S.Pat. No. 6,137,312; which is a continuation of U.S. application Ser. No.08/803,343 filed Feb. 20, 1997 and issued as U.S. Pat. No. 5,910,734.

TECHNICAL FIELD

[0002] This invention relates generally to electronic devices and, morespecifically, to a voltage level translator circuit used in anelectronic device.

BACKGROUND OF THE INVENTION

[0003] There are many instances involving integrated devices wherevoltage level translator circuits are needed to interface betweenoperations circuits that function at different voltage levels. Oneoperations circuit, for example, may transmit high signals based on asource voltage V_(CC). However, a second operations circuit receivingsignals from the first might only recognize high signals at a greatervoltage V_(CC)′. Therefore, a translator circuit is electricallyinterposed between the two operations circuits to receive a signal fromthe first and, if it is a high signal, to output a signal with an evenhigher voltage V_(CCP) that will properly register as a high signal inthe second circuit.

[0004] One example of a translator in the prior art achieves this resultin two distinct charging steps interrupted by a delay. As an inputsignal changes from low to high, this first prior art translator willbegin to charge its output signal to V_(CC). A portion of thetranslator's circuitry, however, does not immediately register thechange in the input signal due to a delaying element incorporated intothe translator. Once the intermediate step of charging the output toV_(CC) is complete, the delaying element finally transmits the changedinput to the remaining circuitry, which then completes the translationprocess by charging the output from V_(CC) to V_(CCP).

[0005] Such a translator, however, requires several transistors as wellas logic devices, resulting in a relatively large circuit, which runscontrary to the desired goal of saving die space. Further, it should benoted that the proper delaying element must be chosen in advance ofusing the translator in non-test operations. If the delay is not longenough to allow the output signal to initially charge to V_(CC), a newdelaying device must be chosen to accommodate the translator circuit.Conversely, too long of a delay runs contrary to the desired goal ofquick circuit operations. Therefore, it would be desirable to have atranslator that is not only smaller but is also capable of translatingan input signal at a faster rate without having to pick-and-choose theproper delaying element.

[0006] A second translator in the prior art attempts to do just that bydirectly driving its output to V_(CCP), with no transition stage atV_(CC). While this second prior art translator is smaller and fasterthan the first, one of ordinary skill in the art can appreciate that thedirect translation to V_(CCP) requires a larger charge pump than oneused in the two stage translator. As a result, the larger charge pumpuses more of the available operating current. Given the inefficiency interms of a charge pump's ability to use operating current, a directtranslation to V_(CCP) is not be desirable in certain applications.Therefore, it would be a major advance in the art to have a translatorthat is smaller and faster than the first prior art example, yet wouldallow charging to an intermediate voltage and then to V_(CCP) in orderto avoid the inefficiency of the large charge pump used in the secondprior art example.

SUMMARY OF THE INVENTION

[0007] Accordingly, the present invention concerns a translator thatprovides an output signal having a generally consistent transition froman initial voltage to a secondary voltage and, eventually, to a finalvoltage, in response to a changing input signal. In one preferredembodiment, the translator is configured to sense when its output loadis approaching a charge of magnitude V_(CC). This embodiment is furtherconfigured to automatically begin charging the output load to V_(CCP) ator around that time without the use of a delaying element. One advantageof this embodiment is that it is smaller and faster than prior arttranslators that operate using a discrete two-stage process to output aV_(CCP) signal. A further advantage of this embodiment is that it usesless current than prior art translators that directly charge an outputload to V_(CCP).

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 depicts an example of a translator as used in the priorart.

[0009]FIG. 2 is a cross-sectional view of a p-channel transistor whichmay be used in prior art as well as in an exemplary embodiment of thepresent invention.

[0010]FIG. 3 illustrates a second translator used in the prior art.

[0011]FIG. 4 is a schematic diagram of an exemplary embodiment inaccordance with the present invention.

[0012]FIG. 5 is a graph illustrating output voltage over time of theprior art translator of FIG. 1 as compared to an exemplary embodiment inaccordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0013]FIG. 1 illustrates the two-stage translator found in the priorart. An input signal IN enters a first inverter 10 and the output isconnected to three separate paths. First, the inverted signal passesthrough a second inverter 12. The output of this second inverter 12 iscoupled to the first input of a first NAND gate 14. The output of thesecond inverter 12 also couples to a delaying element 16, which outputsto a third inverter 18. The third inverter 18, in turn, has an outputcoupled to a second input of the first NAND gate 14. The output of thefirst NAND gate 14 serves as the input for a first circuit portion 20.The first circuit portion 20 is comprised of a p-channel transistor Q101with a source coupled to V_(CCP) and a drain coupled to the drain of ann-channel transistor Q102. The source of transistor Q102, in turn,couples to ground. The two coupled drains serve as an output for thefirst circuit portion 20 and are also connected to the gate of anotherp-channel transistor Q103, which also has a source connected to V_(CCP).Further, the transistor Q103 has a drain attached to the drain ofanother n-channel transistor Q104 having a grounded source. The coupleddrains of Q103 and Q104 attach to the gate of Q101. The output of thefirst NAND gate 14 drives the gate of transistor Q102. The first circuitportion 20 is further comprised of a fourth inverter 22, which alsoreceives the output of the first NAND gate 14 and inverts that signalbefore it reaches the gate of transistor Q104. The output of the firstcircuit portion 20 drives the gate of an n-channel transistor Q105,which has a drain coupled to V_(CC) and a source coupled to the mainoutput node 24.

[0014] The output of first inverter 10 also couples to a first input ofa NOR gate 26. The NOR gate 26 receives a second input from the thirdinverter 18. The output of the NOR gate 26 enters a second circuitportion 28. This second circuit portion is comprised of an n-channeltransistor Q106 that is driven by the output of NOR gate 26. TransistorQ106 also has a source coupled to ground and a drain coupled to a nodeA. The output of NOR gate 26 also couples to the source of an n-channeltransistor Q107, which is driven by V_(CC) and has a drain coupled tothe source of another n-channel transistor Q108 at node B. TransistorQ108 is driven by V_(CCP) and has a drain that couples at node C to thedrain of a p-channel transistor Q109. The source of transistor Q109 isattached to V_(CCP). The coupled drains of Q109 and Q108 are connectedto the gate of another p-channel transistor Q109, which also has asource attached to V_(CCP). By way of node D, the drain of transistorQ110 is coupled to the gate of transistor Q109, as well as to node A.Node A represents the output of the second circuit portion 28, andconnects to the gate of a p-channel transistor Q111. The source oftransistor Q111 connects to V_(CCP) and the drain of Q111 connects tothe main output node 24. Node A also connects to a first input of asecond NAND gate 30.

[0015] Finally, the output of first inverter 10 acts as a second inputfor the second NAND gate 30. The output of this second NAND gate 30passes through a fifth inverter 32 and drives an n-channel transistorQ112. Transistor Q112 has a source coupled to ground and a drain coupledto the main output node 24. Output node 24 is also coupled to a pathconfigured to carry an output signal OUT. A final matter of couplingthis prior art translator is illustrated in FIG. 2. For every p-channeltransistor, an n-well 34 within a p-region 36 is coupled to V_(CCP) atnode 38 to provide the proper back bias.

[0016] The discrete two-step operation of this translator is bestillustrated by examining its functions as IN changes from a low to highsignal. The initial low signal from IN results in a high signal outputfrom the first inverter 10. This high signal is again changed at thesecond inverter 12 to a low signal, which is input to the first NANDgate 14 and the delaying element 16. At this point, the signal IN hasremained low long enough for the delay element 16 to transmit the lowsignal to the third inverter 18, which outputs a high signal. This highsignal combines with the low signal from the second inverter 12 in theNAND gate 14. The resulting high signal enters the first circuit portion20 and turns on transistor Q102. Further, the high signal is inverted bythe fourth inverter 22, and the low signal output turns off transistorQ104. With transistor Q102 on, the gate of transistor Q103 is grounded,thereby turning on Q103. Because Q104's off state prevents Q103's signalfrom grounding, Q103 instead transmits a high signal to Q101's gate,turning Q101 off. In addition, QIOl's off state and Q102's on stateresult in a low signal output from the first circuit portion 20. Thislow signal turns off transistor Q105, isolating V_(CC) from the mainoutput node 24.

[0017] Meanwhile, the high signal from the third inverter 18 combineswith the high signal from the first inverter 10 at the NOR gate 26,which outputs a low signal to the second circuit portion 28. This lowsignal turns off transistor Q106. In doing so, node A is isolated fromground. Moreover, the low signal induces a corresponding low voltage atnode C, which consequently turns on transistor Q110. As a result,transistor Q110 transmits a high signal to transistor Q109, turning Q109off. This high signal also reaches node A and is output from the secondcircuit portion 28. The high signal turns off transistor Q111, isolatingV_(CCP) from the main output node 24.

[0018] The high signal from node A combines with the high signal fromthe first inverter 10 at the second NAND gate 30. The low signal fromthe NAND gate 30 is changed by the fifth inverter 32, and the highsignal from the fifth inverter 32 turns on Q112, grounding any signalsthat reach the main output node 24. Thus, the low signal IN causes a lowsignal OUT.

[0019] As the IN signal changes from a low to a high signal, the firstinverter 10 outputs a low signal and, hence, the second inverter 12outputs a high signal. The first NAND gate 14 receives this high signalas a first input. However, the new high signal is held up by thedelaying element 16 and, as a result, the third inverter 18 temporarilycontinues to output a high signal to the second input of the first NANDgate 14. Receiving two high signals, the first NAND gate 14 transmits alow signal to the first circuit portion 20. This low signal turns offtransistor Q102. Further, the low signal passes through the fourthinverter 22 and the resulting high signal turns on transistor Q104,which provides a path to ground. This grounding turns on transistorQ101, which provides a path from V_(CCP). With transistor Q102 off, theV_(CCP) signal from Q101 has no path to ground and is therefore divertedto the gate of transistor Q103, turning off Q103. The V_(CCP) signal isalso transmitted to the gate of Q105, thereby turning on Q105. Withtransistor Q105 on, the V_(CC) signal coupled to the drain of transistorQ105 is able to reach the main output node 24. It should be noted thatthis configuration allows a full V_(CC) signal to be transmitted. Iftransistor Q105 were driven by a mere V_(CC) signal, only a signal ofmagnitude V_(CC)-V_(t) could pass through transistor Q105, where V_(t)is the voltage threshold of transistor Q105.

[0020] Because of the high signal that is temporarily transmitted fromthe third inverter 18, the NOR gate 26, receiving this high signal aswell as the low signal from the first inverter 10, continues to send outa low signal to the second circuit portion 28. As a result, the state ofthe second circuit portion 28 does not change: a high signal at node A(1) turns off transistor Q111, thereby isolating V_(CCP) from the mainoutput node; and (2) acts as one input for the second NAND gate 30. Theother input for the second NAND gate 30 is the low signal from the firstinverter 10. The resulting high signal is inverted by the fifth inverter32 so that the final low signal turns off transistor Q112, preventingany output signals from grounding at that point. Therefore, during thistransition phase, while the delaying element 16 is postponing the changeof signals, the translator's output signal OUT increases to V_(CC).

[0021] After a time determined by the configuration of the delay element16, the high signal output from the second inverter 12 reaches the thirdinverter 18, thereby triggering the second stage of translation. Thefirst NAND gate 14 accepts the low signal from the third inverter 18 andthe high signal from the second inverter 12. The resulting high signalfrom the first NAND gate 14 returns the first circuit portion 20 to thestate originally described, with transistors Q102 and Q103 on,transistors Q101 and Q104 off, and a low signal output from the firstcircuit portion 20 that turns off transistor Q105. With transistor Q105off, V_(CC) can no longer reach the main output node 24.

[0022] At the same time, however, the newly generated low signal fromthe third inverter 18, in combination with the low signal from the firstinverter 10, results in a high signal output from the NOR gate 26. Thisallows transistor Q107 to push node B to V_(CC)-V_(t). Node C is alsopushed to this level, which partially turns off transistor Q110. Becausea full V_(CC) signal is not applied to transistor Q110, Q110 continuesto pass some current. However, the high signal from the NOR gate 26 alsoturns on transistor Q106, which is configured to be large enough tooverdrive Q110. With transistor Q106 on, a path to ground is providedfor nodes A and D. Node D's connection to ground turns on Q109, which inturn allows a V_(CCP) signal to reach the gate of transistor Q110through node C, turning off transistor Q110 completely. Node A'sconnection to ground turns on Q111, allowing a V_(CCP) signal to reachthe main output node 24.

[0023] Grounded node A further provides a low signal for the second NANDgate 30, which also accepts the low signal from the first inverter 10.The high signal output from the second NAND gate 30 is inverted by thefifth inverter 32 so that a low signal maintains transistor Q112'soff-state. Thus, the V_(CCP) signal originating at transistor Q111 istransmitted as the translator's output signal OUT. In this way, a highinput signal is translated into a signal of magnitude V_(CCP).

[0024] In translating an IN signal changing from high to low, thetranslator circuit is initially at the state described immediatelyabove: the V_(CC) signal is isolated because transistor Q105 is off; adirect path to ground is not available because transistor Q112 is off;and with transistor Q111 on, V_(CCP) is output as the translator's OUTsignal. As IN transmits a low signal, the first inverter 10 sends a highsignal to the second inverter 12. The second inverter 12 transmits a lowsignal to the first NAND gate 14. However, because the low signal fromthe second inverter 12 has not yet cleared the delaying element 16, thethird inverter 18 still outputs a low signal for the first NAND gate 14.Given these two low signals, the first NAND gate 14 continues to send ahigh signal to the first circuit portion 20. It follows that the firstcircuit portion 20 continues to send a low signal to Q105 and isolateV_(CC) from the main output node 24.

[0025] Nevertheless, the high signal from the first inverter 10 doeschange the output from the NOR gate 26. The high signal from the firstinverter 10 plus the remaining low output from the third inverter 18causes the NOR gate 26 to send a low signal to the second circuitportion 28. This turns off transistor Q106, isolating the drain of Q110and the gate of Q109 from ground. Further, a low signal is thentransmitted through node C to transistor Q110, turning on thattransistor. A V_(CCP) signal then passes through transistor Q111 andnode D to transistor Q109, turning it off. Further, this V_(CCP) signaltransmits to node A, turning off transistor Q111 and isolatingV_(CCP)from the main output node 24.

[0026] The high signal from node A also enters the second NAND gate 30,which also receives the high signal from the second inverter 12. Theresult from the second NAND gate 30 is a low signal, which is invertedby the fifth inverter 32. The output high signal turns on transistorQ112, which grounds the main output node 24 and, thus, the signal OUT.

[0027] Moreover, the transition of OUT to a low signal is not affectedby the function of the delaying element 16. Even after the thirdinverter 18 receives the low signal from the second inverter 12, theresulting high signal does not change the input to the first circuitportion 20. Having received a low signal from the second inverter 12 inaddition to the new high signal from the third inverter 18, the firstNAND gate 14 continues to send a high signal to the first circuitportion 20. Similarly, the NOR gate continues to send a low signal tothe second circuit portion 28. Thus the V_(CC) and V_(CCP) signalscontinue to be isolated and the signal OUT continues to be pulled toground through transistor Q112.

[0028] In FIG. 5, line P graphically demonstrates the operation of thisprior art translator. The right portion of line P represents thetranslation of an IN signal going from high to low voltage. Therelatively smooth transition indicates that OUT is not affected by thedelaying element in a high to low operation.

[0029] The left side of the graph, however, clearly illustrates the twostage process required to translate a signal IN going from a low to highvoltage. Line P demonstrates one transition from ground to V_(CC). Theleveling slope of line P occurs as OUT approaches V_(CC) but thedelaying element 16 has not yet allowed V_(CCP) to couple to the mainoutput node 24. Once the delay is over, the signal OUT then once againbegins to increase in voltage until V_(CCP) is reached.

[0030]FIG. 3 illustrates the smaller, faster circuit that translates alow-to-high signal directly to V_(CCP), without the use of a transitoryV_(CC) source. This translator is essentially a paired-down version ofthe first translator, with only the second circuit portion 28 and thefirst inverter 10 remaining. As a result, this translator operates in amanner similar to that second circuit portion 28. Given a low signal IN,the first inverter 10 sends out a high signal. This high signal allowstransistor Q107 to push node B to V_(CC)-V_(t). Node C is also pushed tothat level, thereby partially turning off transistor Q110. The highsignal from the first inverter 10 also turns on transistor Q106. Havingbeen configured to be able to overdrive transistor Q110, transistor Q106grounds any signal passing through transistor Q110. This creates a lowvoltage at node D, which turns on transistor Q109. The resulting V_(CCP)signal completely turns off transistor Q110. With node A also coupled toground via transistor Q106, this translator's output signal OUT is a lowsignal.

[0031] As the signal IN increases to a high signal, the first inverter10 transmits a low signal that turns off transistor Q106. At this stage,node C carries a low signal to transistor Q110, which turns onaccordingly. With no path to ground through transistor Q106, a V_(CCP)signal travels through transistor Q110 and node D to the gate oftransistor Q109. This V_(CCP) signal turns off Q109. Further, thisV_(CCP) signal travels to node A and ultimately serves as the outputsignal OUT. Thus, as a high signal is input, the translator drives itsload directly to V_(CCP), with no transition stage involving V_(CC).Should signal IN make the transition from a high signal back to a lowsignal, the translator would return to the state originally describedabove.

[0032]FIG. 4 illustrates a preferred embodiment of the currentinvention. An input signal IN leads to a primary inverter 40. The outputof the primary inverter couples to the gate of a p-channel transistorQ201 and the gate of an n-channel transistor Q202. In addition to havingcoupled gates, the drains of transistors Q201 and Q202 are coupled toeach other. The coupled drains are in turn connected to a node E. Thesource of transistor Q202 is coupled to ground and the source oftransistor Q201 is coupled at a node F to the drain of another p-channeltransistor Q203. Transistor Q203 has a source coupled to a sourcevoltage V_(CC). Further, as described earlier and illustrated in FIG. 2,transistor Q203, as well as every other p-channel transistor in thisexemplary embodiment, has an n-well 34 within a p-region 36 is coupledto V_(CCP)at node 38 to provide the proper back bias.

[0033] It should also be noted that the values of V_(CC) and V_(CCP) inthis exemplary embodiment may not necessarily have the same values asdiscussed in the prior art translators. Further, it should be notedthat, while this invention can be coupled to various voltage sources, novoltage source is claimed as part of the invention.

[0034] Returning to the primary inverter 40, its output drives thecoupled gates of another pair of transistors: p-channel transistor Q204and n-channel transistor Q205. The drains of transistors Q204 and 205join at a node G. The source of transistor Q205 is coupled to ground andthe source of transistor Q204 is coupled to node E. In addition, node Gis coupled to the gate of transistor Q203. The output of primaryinverter 40 also serves as input for a secondary inverter 42.

[0035] This exemplary embodiment also contains three transistors, Q206,Q207, and Q208, coupled in series. Transistor Q206 is a p-channeltransistor with a source coupled to V_(CCP) and a drain coupled to thedrain of n-channel transistor Q207. The source of transistor Q207 iscoupled to the drain of n-channel transistor Q208, whose source couplesto ground. The gate of transistor Q206 is connected to node G; the gateof transistor Q207 is connected to the output of the secondary inverter42; and the gate of transistor Q208 is connected to node E. Finally, thecoupled drains of transistors Q206 and Q207 drive a p-channel transistorQ209. The source of transistor Q209 is coupled to V_(CCP) and the drainof Q209 is coupled to an output node H. Output node H is also connectedto node E and carries the translator's output signal OUT.

[0036] Once again, the operation of this exemplary circuit is bestdemonstrated by examining its function as IN changes from a low to ahigh signal. The initial low signal IN is inverted by the by the primaryinverter 40. The resulting high signal turns on transistor Q202 butturns off transistor Q201. Further, with Q202 providing a path to groundfor output node H, OUT is a low signal. Additionally, Q202's activationresults in a low voltage signal passing through node E to transistorQ208, turning that transistor off as well.

[0037] The high signal output from the primary inverter 40 also turnsoff transistor Q204 even as it turns on transistor Q205. As Q205provides a path to ground, the resulting low voltage at node G turns onQ203. As a result, node F is pushed to V_(CC). With Q201 in an offstate, however, the V_(CC) charge is isolated from the rest of thecircuit. The low voltage at node G also turns on transistor Q206.

[0038] The high signal from the primary inverter 40 is inverted by thesecondary inverter 42, thereby turning off transistor Q207. Thus, withtransistor Q206 on and transistors Q207 and Q208 off, a V_(CCP) signaldrives transistor Q209, turning off Q209 as well. Therefore, with INtransmitting a low signal, OUT also transmits a low signal, as it iscoupled to ground through output node H and transistor Q202. Moreover,V_(CCP) is isolated from the circuit, but a V_(CC) charge is storedwithin the circuit in anticipation of future changes in the IN signal.

[0039] As the signal IN increases to high, the V_(CC) signal from node Freaches output node H. The manner in which this takes place begins asthe high IN signal is inverted to a low signal by the primary inverter40. This low signal turns off transistor Q202 and turns on transistorQ201. Thus, the V_(CC) signal at node F is diverted through nodes E andH as the OUT signal.

[0040] However, even as OUT approaches a potential of V_(CC), thetranslator is operating to isolate the V_(CC) source. The low signalfrom the primary inverter 40 turns on transistor Q204 and turns offtransistor Q205. Thus, the high signal from node E is transmitted by wayof the source of transistor Q204 and through node G to the gate oftransistor Q203, turning off transistor Q203. As a result, V_(CC) iseventually no longer able to transmit through transistor Q203.

[0041] Nevertheless, the same operations that isolate V_(CC)simultaneously function to couple V_(CCP) to output node H. The highsignal at node G turns off transistor Q206. The low signal from theprimary inverter 40 is inverted by the secondary inverter 42 and theresulting high signal turns on transistor Q207. Subsequently, the highsignal from node E turns on transistor Q208. The states of these threetransistors cause the coupled drains of transistors Q206 and Q207 tosend a low signal to transistor Q209. This turns on Q209 and allowV_(CCP) to charge output node H.

[0042] Thus, while the input signal IN is low, the translator preparesto transmit a V_(CC) signal. As IN increases, the ability of V_(CC) toreach output node H increases. As the potential of OUT approaches theV_(CC) level, the translator automatically operates to gradually shutoff V_(CC) while coupling V_(CCP) to output node H. The result is asmooth transition of OUT from a low signal of 0 volts to a V_(CC) signaland, finally, to a high signal of magnitude V_(CCP). The smoothtransition allowed by this invention can be seen in line I of FIG. 5.The advantage of this embodiment over the first prior art example isparticularly evident on the left part of the graph, denoting the outputsignal OUT in the event of a low to high IN signal. Specifically, line Idemonstrates that the speed of this invention is not limited by thepresence of a delaying element. Rather, this exemplary embodiment isconfigured to automatically provide additional charging when the outputapproaches the desired intermediate voltage. Further, because thisembodiment allows for an intermediate boost to V_(CC), there is no needfor the inefficiently large charge pump that must be used in the secondprior art translator. As a result, this embodiment uses less operatingcurrent that does the second prior art translator.

[0043] If the signal IN transitions from high to low, then the circuitfor this embodiment returns to the state first described: transistorQ202 turns on, grounding the output signal; transistor Q209 turns off,isolating V_(CCP); transistor Q201 turns off, isolating V_(CC) at nodeF; and transistor Q203 turns on to charge node F to V_(CC) inanticipation of the next low-to-high signal. As shown by the right sideof the graph in FIG. 5, although the first prior art translator is notencumbered by the delaying element in the high-to-low transition, thisembodiment of the current invention operates faster because it is asmaller circuit.

[0044] Finally, one of ordinary skill in the art can appreciate that,although a specific embodiment of this invention has been describedabove for purposes of illustration, various modifications may be madewithout departing from the spirit and scope of the invention. Asdemonstrated in U.S. Pat. No. 5,136,190, by Chern et al., for example,the proper number of inverters would allow the translator to output aV_(CCP) signal in response to a high-to-low input signal change ratherthan a low-to-high change. As another example, an additional n-channeltransistor could be interposed between transistor Q203 and V_(CC).Driving this additional transistor at V_(CCP) would ensure that a signalof magnitude V_(CC) would not be transmitted through transistor Q203until V_(CCP) exceeded V_(CC). Moreover, a circuit similar to theembodiments disclosed above could be configured to translate an inputsignal having a low voltage into an output signal having even a lowervoltage Accordingly, the invention is not limited except as stated inthe claims.

What is claimed is:
 1. A translator comprising: an output node; a firstelement coupled to said output node and configured to receive a firstvoltage potential; a second element coupled to said output node andconfigured to receive a second voltage potential; and a progressiveselection element coupled to said first element, said output node, andto said second element, further comprising: a sense component coupled tosaid output node and configured to detect a voltage potential of saidoutput node, and a drive component coupled to said first element, saidsecond element, and to said sense component, wherein said drivecomponent is configured to selectively drive said first element and saidsecond element, and said drive component is further configured toincreasingly drive said second element as said voltage potential of saidoutput node approaches said first voltage potential.
 2. The translatorof claim 1, wherein said drive component is further configured todecreasingly drive said first element as said voltage potential of saidoutput node approaches said first voltage potential.
 3. The translatorof claim 2, wherein said second element is configured to raise saidvoltage potential of said output node from a level greater than groundpotential.
 4. The translator of claim 3, wherein said second element isconfigured to raise said voltage potential of said output node from alevel generally equal to said first voltage potential.
 5. A translatorhaving an input terminal and an output terminal, comprising: an outputground circuit coupled to said input terminal and said output terminal,wherein said output ground circuit is configured to ground said outputterminal in response to a first signal received at said input terminaland further configured to isolate said output terminal from ground inresponse to a second signal received at said input terminal; an interimvoltage storage circuit having a storage node and coupled to said inputterminal and to an interim voltage source, wherein said interim voltagestorage circuit is configured to provide electrical communicationbetween said interim voltage source and said storage node in response tosaid first signal; an interim voltage charge circuit coupled to saidinput terminal, said interim voltage storage circuit, and to said outputterminal, wherein said interim voltage charge circuit is configured tocouple said storage node to said output terminal in response to saidsecond signal; an interim voltage isolation circuit coupled to saidinput terminal, said interim voltage source, and to said interim voltagestorage circuit, wherein said interim voltage isolation circuit isconfigured to halt electrical communication between said interim voltagesource and said storage node in response to said storage node beingcoupled to said output terminal; and a final voltage circuit coupled tosaid input terminal, said output terminal, and a final voltage source;wherein said final voltage circuit is configured to: isolate said finalvoltage source in response to said first signal, and link said finalvoltage source to said output terminal in response to said storage nodebeing coupled to said output terminal.
 6. The translator of claim 5,wherein at least one pair of circuits selected from said output groundcircuit, said interim voltage storage circuit, said interim voltagecharge circuit, said interim voltage isolation circuit, and said finalvoltage circuit contain common elements.
 7. The translator of claim 6,wherein said common elements are transistors.
 8. A device configured toreceive an input signal having a voltage V_(CC) and respond bytransmitting an output signal having a higher voltage V_(CCP),comprising: an output node; an input node configured to receive saidinput signal; a V_(CCP) charging circuit coupled to said output node andconfigured to receive a voltage source V_(CCP); a V_(CC) generationcircuit configured to receive a voltage source V_(CC); an activationcircuit coupled to said V_(CCP) charging circuit and said V_(CC)generation circuit and configured to selectively transmit an activationsignal to said V_(CCP) charging circuit and said V_(CC) generationcircuit; and a main circuit coupled to said V_(CCP) charging circuit,said V_(CC) generation circuit, said activation circuit, said inputnode, and said output node, comprising: a driver circuit coupled to saidV_(CCP) charging circuit and said input node and configured to transmita driving signal in response to said input signal, an activation circuitpowering device coupled to said activation circuit and said input nodeand configured to deliver a supply signal in response to said inputsignal, a first electrical communication enabler coupled to said inputnode, electrically interposed between said voltage source V_(CC) andsaid output node, and configured to function in response to said inputsignal, and an output node ground device coupled to said output node andsaid input node and configured to function in response to an absence ofsaid input signal.
 9. The device in claim 8, wherein said V_(CCP)charging circuit further comprises: a V_(CCP) coupler circuit connectedto said output node and configured to receive said voltage sourceV_(CCP), further comprising: a coupler terminal configured to receive acoupler signal, and a second electrical communication enabler coupled tosaid voltage source V_(CCP) and to said output node and configured tofunction in response to said coupler signal received at said couplerterminal; and a V_(CCP) operations circuit coupled to said activationcircuit, said main circuit, said input node, and to said couplerterminal of said V_(CCP) coupler circuit, wherein said V_(CCP)operations circuit is configured to receive said voltage source V_(CCP)and further configured to transmit said coupler signal in response tosaid activation signal from said activation circuit, said driving signalfrom said driver circuit, and from said input signal.
 10. The device inclaim 9, wherein said coupler signal has a voltage lower than saidvoltage V_(CCP).
 11. The device in claim 10, wherein said coupler signalhas a voltage lower than said voltage V_(CC).
 12. The device in claim11, wherein said coupler signal is generally 0 volts.
 13. The device inclaim 9, wherein said V_(CCP) operations circuit further comprises: avoltage shut-off circuit coupled to said activation circuit and to saidcoupler terminal of said V_(CCP) coupler circuit, and configured toreceive said voltage source V_(CCP), wherein said voltage shut-offcircuit is configured to prevent communication between said voltagesource V_(CCP)and said coupler terminal in response to said activationsignal from said activation circuit; and a ground communication circuitcoupled to said input node, said main circuit, said voltage shut-offcircuit, and to said coupler terminal of said V_(CCP)coupler circuit,and configured to provide grounding communication for said couplerterminal in response to a combination of said activation signal and saidinput signal.
 14. The device in claim 13, wherein said activationsignal, said driving signal, and said input signal are generallyconcurrent.
 15. A translation device having an input node and an outputnode, comprising: an activation circuit coupled to: said input node; afirst charging circuit coupled to a first voltage node configured toreceive a first voltage source; and a second charging circuit coupled toa second voltage node configured to receive a second voltage source;wherein said activation circuit comprises: a first connection devicecoupled to said first charging circuit and to said output node, whereinsaid first connection device is configured to prevent electricalcommunication in response to a first signal received at said input node,and allow electrical communication in response to a second signalreceived at said input node, a source disconnection device coupled tosaid first charging circuit and configured to prevent electricalcommunication with said first voltage node in response to said secondsignal, and a second connection device coupled to said second chargingcircuit and to said output node, wherein said second connection deviceis configured to: prevent electrical communication in response to saidfirst signal received at said input node, and allow electricalcommunication in response to said second signal.
 16. The translationdevice of claim 15, wherein said second voltage node has a highervoltage potential than said first voltage node.
 17. A translatorreceiving an input signal selectively transmitting a first value and asecond value, comprising: an output terminal; a first stage chargecircuit selectively coupled to said output terminal and configured tocouple to a first node having a first potential; a second stage chargecircuit selectively coupled to said output terminal and configured tocouple to a second node having a second potential; and a stage selectioncircuit comprising: a connection circuit coupled to said first stagecharge circuit and to said output terminal and configured to activate inresponse to said second value, a progressive discharge circuit coupledto said first stage charge circuit and to said output terminal, whereinsaid progressive discharge circuit is configured to initiate in responseto a potential of said output terminal generally approaching said firstpotential, and a progressive enable circuit coupled to said second stagecharge circuit and to said output terminal, wherein said progressiveenable circuit is configured to initiate in response to said potentialof said output terminal generally approaching said first potential. 18.The translator of claim 17, wherein an operation of said progressivedischarge circuit proceeds in a direct proportion to an operation ofsaid progressive enable circuit.
 19. A translating circuit having aninput terminal configured to receive a first signal and a second signal,comprising: a first voltage device coupled to said input terminal andconfigured to initially hold a first potential; a second voltage devicecoupled to said input terminal and configured to hold a secondpotential; and an output device selectively coupled to said firstvoltage device, said second voltage device, and to ground, comprising: aground coupler configured to operate in response to said first signal, afirst voltage coupler connected to said first voltage device andconfigured to operate in response to said second signal, and a secondvoltage coupler connected to said second voltage device and configuredto operate in response to a connection between said first voltage deviceand said output device.
 20. The translating circuit in claim 19, whereinsaid output device is configured to disconnect from ground in responseto said second signal.
 21. The translating circuit in claim 20, whereinsaid first voltage device comprises a potential discharge device, and anoperation of said potential discharge device is concurrent with anoperation of said second voltage coupler.
 22. A translator configured tochange a potential of an output pathway in response to a first change ofan input signal, comprising: an input pathway configured to receive saidinput signal; an output ground device coupled to said output pathway andto said input pathway; a first restriction device coupled to said outputpathway, to said input pathway, and to a first voltage node configuredto accept a first voltage source; a second restriction device coupled tosaid output pathway, said input pathway, and to an internal node; and anaccess device coupled to said internal node, said output ground device,and to a second voltage node configured to receive a second voltagesource; wherein said output ground device, said first restrictiondevice, and said second restriction device are configured to activate inresponse to said first change of said input signal, and said accessdevice is configured to activate in response to an activation of saidoutput ground device.
 23. The translator in claim 22, further configuredto change said potential of said output pathway in response to a secondchange in said input signal, wherein: said output ground device, saidfirst restriction device, and said second restriction device areconfigured to deactivate in response to said second change of said inputsignal; and said access device is configured to deactivate in responseto a deactivation of said output ground device.
 24. The translator inclaim 23, further comprising a drive device comprising: a supply pathwaycoupled to said output ground device and to said second restrictiondevice; a drive pathway coupled to said access device and to said firstrestriction device; and a selection device coupled to said supplypathway, said drive pathway, and said input pathway; wherein said drivedevice is configured to activate said access device and said firstrestriction device in response to said first change of said inputsignal.
 25. A voltage level translator, comprising: an input terminalconfigured to receive an input signal having a first value and a secondvalue; a grounding device coupled to said input terminal and an outputterminal, wherein said grounding device is: configured to allowelectrical communication between said output terminal and ground inresponse to said first value of said input signal, and furtherconfigured to prevent electrical communication between said outputterminal and ground in response to said second value; a V_(CC) outputdevice coupled to said input terminal and to said grounding device,wherein said V_(CC) output device is configured to: receive a voltagesource V_(CC), halt electrical communication with said grounding devicein response to said first value, couple said voltage source V_(CC) tosaid output terminal through said grounding device in response to saidsecond value, and halt electrical communication with said groundingdevice in response to electrical communication between said voltagesource V_(CC) and said output terminal; and a V_(CCP) output devicecoupled to said input terminal, said output terminal, said groundingdevice, and said V_(CC) output device, wherein said V_(CCP) outputdevice is configured to: receive a voltage source V_(CCP), preventelectrical communication between said voltage source V_(CCP) and saidoutput terminal in response to said first value of said input terminal,and couple said voltage source V_(CCP) to said output terminal inresponse to electrical communication between said voltage source V_(CC)and said output terminal.
 26. The voltage level translator of claim 25,wherein said grounding device comprises: a first voltage-passingcomponent coupled to said input terminal, to said V_(CC) output device,and said output terminal, wherein said first voltage-passing componentis configured to deactivate in response to said first value of saidinput signal and activate in response to said second value; and a firstvoltage-reducing component coupled to said input terminal, said firstvoltage-passing component, said output terminal, and to a ground node,wherein said first voltage-reducing component is configured to activatein response to said first value and deactivate in response to saidsecond value.
 27. The voltage level translator of claim 26, wherein saidV_(CC) output device comprises: a second voltage-passing componentcoupled to said input terminal, said first voltage-passing component,and said first voltage-reducing component, wherein said secondvoltage-passing component is configured to deactivate in response tosaid first value of said input signal and activate in response to saidsecond value; a second voltage-reducing component coupled to said inputterminal and to said second voltage-passing component, and said groundnode, wherein said second voltage-reducing component is configured toactivate in response to said first value and deactivate in response tosaid second value; and a third voltage-passing component coupled to saidsecond voltage-passing component, said second voltage-reducingcomponent, said first voltage-passing component, and a V_(CC) node,wherein said third voltage-passing component is configured to activatein response to an activation of said second voltage-reducing componentand is further configured to deactivate in response to an activation ofsaid second voltage-passing component.
 28. The voltage level translatorof claim 27, wherein said V_(CCP) output device comprises: a fourthvoltage-passing component coupled to said second voltage-passingcomponent, said second voltage-reducing component, and a V_(CCP) node,wherein said fourth voltage-passing component is configured to activatein response to activation of said second voltage-reducing component anddeactivate in response to activation of said second voltage-passingcomponent; a third voltage-reducing component coupled to said fourthvoltage-passing component and to said input terminal, wherein said thirdvoltage-reducing component is configured to deactivate in response tosaid first value of said input signal and to activate in response tosaid second value; a fourth voltage-reducing component coupled to saidthird voltage-reducing component, said first voltage-reducing component,said first voltage-passing component, and said ground node, wherein saidfourth voltage-reducing component is configured to deactivate inresponse to activation of said first voltage-reducing component and toactivate in response to activation of said first voltage-passingcomponent; and a fifth voltage-passing component coupled to a V_(CCP)node, said fourth voltage-passing component, said third voltage-reducingcomponent, and said output terminal, wherein said fifth voltage-passingcomponent is configured to deactivate in response to activation of saidfourth voltage-passing component and to activate in response to:deactivation of said fourth voltage-passing component, activation ofsaid third voltage-reducing component, and activation of said fourthvoltage-reducing component.
 29. The voltage level translator of claim 28further comprising a primary inverter electrically interposed betweensaid input terminal and said first voltage-reducing component and saidfirst voltage-passing component.
 30. The voltage level translator ofclaim 29 further comprising a secondary inverter electrically interposedbetween said primary inverter and said third voltage-reducing component.31. A method of translating a change of an input signal to an outputV_(CCP) signal comprising: charging an output node from a V_(CC) source;approaching a potential of V_(CC) for said output node; detecting saidoutput node approaching said potential of V_(CC); and charging saidoutput node from a V_(CCP) source.
 32. The method in claim 31, furthercomprising a step of ending charging said output node from said V_(CC)source in synchronization with beginning charging said output node fromsaid V_(CCP) source.
 33. A method for preparing a circuit for a signaltranslation, comprising: isolating a first source having a firstpotential from an output pathway; grounding said output pathway; andrestricting a second source having a second potential to an internaltranslator node.
 34. The method in claim 33, wherein said restrictingstep further comprises transmitting a signal of said second potentialthrough at least one circuit device.
 35. The method in claim 34, whereinsaid first potential is higher that said second potential.
 36. A methodof translating a changing input signal, comprising the steps of:initializing a charging of an output pathway with a first voltagesource; reducing a contribution of said first voltage source in saidcharging; and increasing a contribution of a second voltage source insaid charging.
 37. The method in claim 36, wherein: said contribution ofsaid first voltage source represents a first proportion of a totalcharge flow; said contribution of said second voltage source representsa second proportion of said total charge flow; and said total chargeflow remains generally constant while translating.
 38. A method oftranslating a signal changing from a first voltage to a second voltage,comprising the steps of: initiating a primary voltage signal; initiatingan intermediate voltage signal; isolating a source of said intermediatevoltage signal; and initiating a secondary voltage signal; wherein saidsteps of initiating an intermediate voltage signal, isolating a sourceof said intermediate voltage signal, and initiating said secondaryvoltage signal begin generally simultaneously.
 39. A method of sending asignal from a translation circuit, comprising: internally generating afirst voltage; transmitting a first voltage signal; separating a firstvoltage source from said translation circuit; and transmitting a secondvoltage signal.
 40. The method in claim 39 wherein: said step oftransmitting a first voltage signal occurs at a first transmission rate;said step of separating said first voltage source occurs at a separationrate; and said separation rate is generally equal to said firsttransmission rate.
 41. The method of claim 40, wherein said step oftransmitting said second voltage signal occurs at a second transmissionrate; and said second transmission rate is generally equal to saidseparation rate.
 42. A method of sending an output signal to an outputpath of a translator, comprising: receiving an input signal having avalue; generating a first voltage at a first node within saidtranslator; providing a second voltage at a second node; isolating saidfirst node from said output path; isolating said second node from saidoutput path; changing said value of said input signal; using said firstnode as a charge source for said output path; and evenly transitioningfrom said first node to said second node as said charge source for saidoutput path.
 43. A method of translating a change of an input signalcomprising: uninterruptedly charging a translated output from an initialvoltage to a final voltage, wherein said uninterruptedly charging stepfurther comprises: charging said translated output from said initialvoltage to a transitional voltage; and charging said translated outputfrom said transitional voltage to said final voltage.
 44. The method inclaim 43, wherein said transitional voltage is greater than said initialvoltage and less than said final voltage.
 45. A method of charging anoutput path of a translator, comprising the steps of: connecting avoltage source of potential V_(CC) to said translator; enabling acharging of said output path to V_(CC), wherein said enabling stepfurther enables: connecting a voltage source of potential V_(CCP) tosaid output path, and charging said output path to V_(CCP).
 46. Themethod in claim 45, wherein: said charging of said output path to V_(CC)occurs at a V_(CC) charge rate; said charging of said output path toV_(CCP) occurs at a V_(CCP) charge rate; and said V_(CCP) charge rate isgenerally inversely proportional to said V_(CC) charge rate.
 47. Themethod in claim 46, wherein the step of enabling a charging of saidoutput path to V_(CC) further enables a step of disconnecting saidvoltage source of potential V_(CC) from said translator.
 48. The methodin claim 47, wherein disconnecting said voltage source of potentialV_(CC) occurs at the same general time and rate as charging said outputpath to V_(CCP).
 49. A method of providing a voltage level translationto an output, comprising the steps of: applying a first voltagepotential to said output; and consistently shifting toward applying asecond voltage potential to said output.
 50. The method in claim 49wherein: said output has an output voltage level; and said step ofconsistently shifting occurs as said output voltage level approachessaid first voltage potential.
 51. A method of translating a signaltransitioning from an initial voltage to a final voltage, comprising:providing a first electrical communication with a first voltage source;initiating a first voltage output; gradually preventing said firstelectrical communication with said first voltage source; providing asecond electrical communication with a second voltage source; andgradually initiating a second voltage output concurrently with said stepof gradually preventing said first electrical communication.
 52. Amethod of translating an input signal capable of changing potential,comprising: grounding any output transmission in response to a firstpotential change of said input signal; and generating a first chargefrom a first voltage source, wherein said first charge has a voltage ofsaid first potential.
 53. The method in claim 52 further comprising thefollowing steps: transmitting said first charge in response to a secondpotential change in said input signal; preventing electricalcommunication from said first voltage source in response to transmittingsaid first charge; and transmitting a second charge having a secondvoltage in response to transmitting said first charge and in response tosaid second potential change in said input signal.
 54. A method oftranslating a changing voltage signal, comprising: providing electricalcommunication between a first node having a potential and a first chargesource through a first conductive pathway; charging said first node to afirst voltage with said first charge source; charging an output node tosaid first voltage from said first node; discharging to said firstconductive pathway from said first node; discharging to a secondconductive pathway from said first node; disrupting electricalcommunication between said first node and said first charge source bysaid step of discharging to said first conductive pathway; providingelectrical communication between a second charge source and said outputnode through said second conductive pathway; increasing electricalcommunication between said second charge source and said output node assaid potential of said first node decreases; and charging said outputnode to a second voltage with said second charge source.